DISEÑO COMPORTAMENTAL DE NEURONAS DE IMPULSO EN HARDWARE RECONFIGURABLE BASADAS EN EL MODELO DE IZHIKEVICH (BEHAVIORAL DESIGN OF SPIKING NEURONS IN RECONFIGURABLE HARDWARE BASED ON IZHIKEVICH MODEL)

Isaac Macias Mendoza, Juan José Raygoza Panduro, Edwin Christian Becerra Alvares, Mario Jiménez Rodríguez, José Luis González Vidal, José Roberto Reyes Barón

Resumen


Resumen
Los modelos matemáticos de neuronas han logrado ser computacionalmente eficientes y biológicamente plausibles, como es el modelo de Izhikevich. La implementación de neuronas artificiales en hardware se ha extendido en áreas como: control, robótica, entre otros. Sin embargo, migrar un modelo a hardware en un sistema reconfigurable se complica debido a la alta ocupación de recursos lógicos. En este trabajo se presenta el diseño de dos neuronas de impulsos que replican el comportamiento del modelo de Izhikevich y la propuesta de modificación de estas para una funcionalidad más amplia. Se realizan simulando el modelo como sistema dinámico en software con un tiempo de 100 ms, para obtener los valores de iteraciones en los que se generan impulsos. Son implementadas en lenguaje de descripción de hardware utilizando máquinas de estado. Como resultados se obtienen neuronas que ocupan 10 y 13 Flip-Flops de 1536 disponibles en una FPGA Spartan 3.
Palabras Clave: FPGA’s, Modelo de Izhikevich, Neurona de impulso.

Abstract
Mathematical models of neurons have managed to be computationally efficient and biologically plausible like Izhikevich's model. The implementation of artificial neurons in hardware has spread in areas such as: control, robotics, among others. However, migrating a model to hardware in a reconfigurable system is complicated due to the high occupation of logical resources. This work presents the design of two spiking neurons that replicate the behavior of the Izhikevich model and the proposal to modify these for a broader functionality. They are carried out by simulating the model as a dynamic system in software with a time of 100 ms, to obtain the values of iterations in which spikes are generated. They are implemented in hardware description language using state machines. The results are neurons that occupy 10 and 13 Flip Flops out of 1536 available in a Spartan 3 FPGA.
Keywords: FPGA’s, Izhikevich model, Spiking neurons.

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Referencias


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