DISEÑO VLSI DE UN SUMADOR DE PUNTO FLOTANTE USANDO LAS HERRAMIENTAS DE ALLIANCE (VLSI DESIGN OF FLOATING POINT ADDER USING ALIANCE TOOLS)
Resumen
La suma es la operación clave en los sistemas digitales y el sumador de punto flotante se usa con frecuencia para la suma de números reales porque la representación de punto flotante proporciona un amplio rango dinámico. En este artículo se presenta el diseño VLSI (Very Large Scale Integration) de un circuito sumador de punto flotante. El algoritmo se implementó en lenguaje de descripción de hardware VHDL. Posteriormente se utilizan las herramientas de software libre de Alliance para realizar el proceso de síntesis, con el cual se obtuvo el layout del circuito. El diseño presentó un consumo de área de 959,250 , un retardo de 20.8 ns y se utilizaron 4,604 transistores.
Palabras Clave: Área, Diseño VLSI, PF, Retardo, VHDL.
Abstract
Addition is the key operation in digital systems, and floating-point adder is frequently used for real number addition because floating-point representation provides a large dynamic range. This paper presents the VLSI (Very Large Scale Integration) design of a floating point adder circuit. The algorithm was implemented in hardware description language VHDL. Subsequently, Alliance free software tools were used to perform the synthesis process, obtaining the circuit layout in generic units of lambda. The design presented an area consumption of 959,250, a delay of 20.8 ns and 4,604 transistors were used.
Keywords: Area, Delay, Floating point, VHDL, VLSI Design
Texto completo:
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