ALGORITMO DE ENRUTAMIENTO ATENTO A LA ENERGÍA PARA REDES INTRACHIP (ENERGY-AWARE ROUTING ALGORITHM FOR NETWORK ON CHIP)

Arley Villa Salazar, Gustavo Patiño

Resumen


Resumen

Las redes intrachip (Network on Chip, NoC) han sido reconocidas como una solución viable para resolver los desafíos del diseño de sistemas en chip (Systems on Chip, SoC), proporcionando una estructura de comunicación escalable y eficiente para un sistema multiprocesador. Sin embargo, esta solución tiene un alto consumo de energía. Para minimizar dicho consumo, es esencial diseñar un algoritmo de enrutamiento eficiente que permita la administración de energía mientras se maximiza el rendimiento.
Este documento propone un algoritmo de enrutamiento atento a la energía (llamado EA-NoC) que permite optimizar la energía dinámica al determinar la ruta óptima entre origen y destino, evitando el consumo innecesario. Los algoritmos de enrutamiento se simulan en una topología de malla 2D y se comparan con los algoritmos de enrutamiento implementados en el simulador Noxim. Los resultados experimentales muestran que el algoritmo propuesto, mejora en un 28% en promedio el consumo de potencia dinámica en comparación con los algoritmos existentes en la literatura.

Palabras Claves: Algoritmo de Enrutamiento, Atento a la Energía, Multiprocesador, Redes Intrachip, Reducción de Energía.

 

Abstract

Networks on Chip (NoC) have been recognized as a viable solution to solve the challenges of designing Systems on Chip (SoC), providing a scalable and efficient communication structure for multicore systems. However, this solution has high energy consumption. In order to minimize such consumption, it is essential to design an efficient routing algorithm which allows power management while maximizing throughput.
This paper proposes an energy aware routing algorithm (called EA-NoC) that allows optimizing this resource by determining the optimal route between source and destination, avoiding unnecessary energy consumption. The routing algorithms are simulated on a 2D-mesh topology, and compared to the State-of-the-Art routing algorithms implemented in the Noxim simulator. The experimental results show that the proposed algorithm performs 28 % better on average, in terms of dynamic power, compared to the existing algorithms in the literature.

Keywords: Energy-Aware, MPSoC, Network on Chip, Reduction Energy, Routing Algorithm.


Texto completo:

770-788 PDF

Referencias


Achuthan, NR; Caccetta, L: Integer linear programming formulation for a vehicle routing problem. En: European Journal of Operational Research 52 (1991), Nr. 1, p.86-89

Banerjee, Arnab; Mullins, Robert; Moore, Simon: A power and energy exploration of network-on-chip architectures. En: First International Symposium on Networkson-Chip (NOCS'07) IEEE, 2007, p. 163-172

Bell, Shane; Edwards, Bruce; Amann, John; Conlin, Rich; Joyce, Kevin; Leung, Vince; MacKay, John; Reef, Mike; Boa, Leeway; Brown, John [u. a.]: Tile64-processor: A 64-core SoC with mesh interconnect. En: 2008 IEEE International Solid-State Circuits Conference-Digest of Technical Papers IEEE, 2008, p. 88-598

Benini, Luca; De Micheli, Giovanni: Networks on chips: A new SoC paradigm. En: computer 35 (2002), Nr. 1, p. 70-78

Berman, Amit: Power Reduction Techniques for Networks-on-Chip. (2010)

Bianzino, Aruna P.; Chaudet, Claude; Larroca, Federico; Rossi, Dario; Rougier, Jean-Louis: Energy-aware routing: A reality check. En: 2010 IEEE Globecom Workshops IEEE, 2010, p. 1422-1427

Bolla, Raffaele; Bruschi, Roberto; Carrega, Alessandro; Davoli, Franco: Green networking with packet processing engines: Modeling and optimization. En: IEEE/ACM Transactions on Networking (TON) 22 (2014), Nr. 1, p. 110-123

Borkar, Shekhar: Thousand core chips a technology perspective. En: 2007 44th ACM/IEEE Design Automation Conference IEEE, 2007, p. 746-749

Catania, Vincenzo; Mineo, Andrea; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide: Cycle-accurate network on chip simulation with noxim. En: ACM Transactions on Modeling and Computer Simulation (TOMACS) 27 (2016), Nr.1, p4

Chiaraviglio, Luca; Wiatr, Pawel; Monti, Paolo; Chen, Jiajia; Lorincz, Josip; Idzikowski, Filip; Listanti, Marco; Wosinska, Lena: Is green networking beneficial in terms of device lifetime? En: IEEE Communications Magazine 53 (2015), Nr. 5, p. 232-240

Das, Sourav; Doppa, Janardhan R.; Pande, Partha P.; Chakrabarty, Krishnendu: Design-space exploration and optimization of an energy-efficient and reliable 3-D smallworld network-on-chip. En: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36 (2017), Nr. 5, p. 719-732

De Micheli, Giovanni; Benini, Luca: Networks on chips: 15 years later. En: Computer (2017), Nr. 5, p. 10-11

Kullu, Pinar; Tosun, Suleyman: Energy-aware and fault-tolerant custom topology design method for network-on-chips. En: Nano Communication Networks 19 (2019), p. 54-66

Mubeen, Saad. Evaluation of source routing for mesh topology network on chip platforms. 2009

Nickolls, John; Dally, William J.: The GPU computing era. En: IEEE micro 30 (2010), Nr. 2, p. 56-69

Patooghy, Ahmad; Sarbazi-Azad, Hamid: Performance comparison of partially adaptive routing algorithms. En: 20th International Conference on Advanced Information Networking and Applications-Volume 1 (AINA'06) Vol. 2 IEEE, 2006, p. 5-pp

Rahaman, Munshi M.; Ghosal, Prasun; Das, Tuhin S.: Latency, Throughput and Power Aware Adaptive NoC Routing on Orthogonal Convex Faulty Region. En: Journal of Circuits, Systems and Computers 28 (2019), Nr. 04, p. 1950055

Reehal, Gursharan K.: Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs, The Ohio State University, Tesis de Grado, 2012

Tsai, Wen-Chung; Lan, Ying-Cherng; Hu, Yu-Hen; Chen, Sao-Jie: Networks on chips: structure and design methodologies. En: Journal of Electrical and Computer Engineering 2012 (2012), p. 2

Wang, Hang-Sheng; Zhu, Xinping; Peh, Li-Shiuan; Malik, Sharad: Orion: a power performance simulator for interconnection networks. En: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture IEEE Computer Society Press, 2002, p. 294-305

Wu, Ji; Dong, Dezun; Wang, Li: NoC power optimization using combined routing algorithms. En: 2017 IEEE/ACIS 16th International Conference on Computer and Information Science (ICIS) IEEE, 2017, p. 299-304

Zhan, Jia; Ouyang, Jin; Ge, Fen; Zhao, Jishen; Xie, Yuan: DimNoC: A dim silicon approach towards power-efficient on-chip network. En: 2015 52nd ACM / EDAC / IEEE Design Automation Conf






URL de la licencia: https://creativecommons.org/licenses/by/3.0/deed.es

Barra de separación

Licencia Creative Commons    Pistas Educativas está bajo la Licencia Creative Commons Atribución 3.0 No portada.    

TECNOLÓGICO NACIONAL DE MÉXICO / INSTITUTO TECNOLÓGICO DE CELAYA

Antonio García Cubas Pte #600 esq. Av. Tecnológico, Celaya, Gto. México

Tel. 461 61 17575 Ext 5450 y 5146

pistaseducativas@itcelaya.edu.mx

http://pistaseducativas.celaya.tecnm.mx/index.php/pistas